Power switches are commonly used to couple a power supply to a device such as a digital logic circuit or a memory cell. FIG. 1 illustrates such a prior art power switch 10 coupled to selectively supply power from a core power supply 12 to a device 14 (e.g., a digital logic circuit, a memory cell, etc.). In the illustrated example, the power switch 10 is implemented by a PMOS field effect transistor. The source of the transistor 10 is coupled to the core power supply 12. The drain of the transistor 10 is coupled to the device 14. The gate of the transistor 10 is coupled to a control circuit that applies an on/off drive signal to switch the transistor 10 between a conducting state and a non-conducting state to supply and/or terminate the supply of power to the device 14.
Power switches such as the switch 10 exhibit undesirable standby leakage current. This standby leakage current is primarily attributable to the drain-source leakage current of the power switch 10. To reduce this leakage current, it has recently been proposed to bias the backgate of the power switch 10 with a voltage greater than the voltage supplied to the source of the switch 10. Biasing the backgate of the power switch 10 in this manner effectively increases the turn-on voltage of the switch 10 and dramatically reduces the leakage current through the switch 10 when the switch 10 is off. Indeed, this technique can reduce the leakage current by a factor of fifty.
It is often the case that an integrated circuit will have two available power supplies, namely, a core voltage supply 12 and an input/output (IO) power supply 16. The IO power supply 16 typically produces a higher voltage than the core supply 12. For example, the IO supply 16 of FIG. 1 produces a voltage of 1.8 volts, whereas the core supply 12 of FIG. 1 produces a voltage of 1.3 volts. The circuit of FIG. 1 takes advantage of the presence of these two power supplies by using the core voltage from the core supply 12 to supply power to the device 14 via the transistor 10, and by using the IO voltage from the IO supply 16 to bias the backgate of the transistor 10. However, at startup, one cannot guarantee that the core voltage 12 will ramp-up before the IO voltage 16. Thus, it is possible that the voltage from the core supply 12 will, at least for a time during startup, be greater than the voltage from the IO supply 16. If the ramp-up sequence of the core supply 12 and the IO supply 16 is such that the core voltage supplied to the source of the transistor 10 sufficiently exceeds the IO voltage applied to the backgate, an undesirable latchup condition can arise.
More specifically, as shown in FIG. 2, the transistor 10 and the device 14 may be formed in the same silicon substrate. Even if proper high voltage spacing between the switch 10 and the device 14 is employed, the well-to-well spacing in such a circuit may be low. Further, no guard ring is placed around the switch 10. As a result, if the core voltage 12 rises more quickly than the IO voltage 16, the pn junction between the source and the substrate/well 20 of the switch 10 may become forward biased. As a result, a latchup condition may occur wherein, instead of current flowing in the desired current path 18 from the source to the drain, the current injected into the substrate/well 20 flows directly into the well of the device 14 via, for example, current path 22. Such a latchup condition may result in damage to the device 14, the switch 10 and/or the power supply 12. Even if no damage results, the device 14 is likely to malfunction. Further, once a latchup condition occurs, it is difficult, if not impossible, to cause the switch 10 to operate properly (i.e., with current flowing from source to drain via path 18) without resetting the device by disconnecting power.